1. Field of the Invention
The invention relates to a system with voltage level adjustment function, and more particularly, to system with voltage level adjustment function accomplished by a level shifter utilizing only one clock to transform potential levels of the clock.
2. Description of the Prior Art
Level shifters are often utilized in all kinds of circuits to define DC levels. Furthermore, signals are often defined according to the DC levels. For example, in LCD fields, external circuits of the LCD panels may be biased by a positive voltage level 5V and a negative voltage level 0V. Inner circuits of the LCD panels may be biased by a positive voltage level 10V and a negative voltage level 0V. Assume that a signal has a 5V(0V) voltage level, which is defined as a digital 1(0) in the external circuits. If the signal is directly inputted into the inner circuits without a transformation, the inner circuits may misinterpret the signal. For example, if the signal 5V has a 1V noise, the signal may have an instant voltage 4V. Therefore, the signal may be regarded as a digital 0 in the inner circuits instead of the wanted digital 1. In other words, an error occurs.
Level shifters are utilized to solve this problem. The level shifters can transform an input signal having a 0V and 5V voltage levels into an output signal having a 10V and −10V voltage levels. After the transformation of the level shifters, misinterpretation of the signal by the inner circuits can be prevented. Therefore, the above-mentioned error does not occur.
In the prior art, the level shifter is driven by two input clock signals. In other words, the output clock signal is generated according to the two input clock signals. But it is well known that if two input clock signals are utilized, more pins need to be utilized in order to receive the input clock signals. The pin number is therefore increased, potentially reducing the reliability of the LCD panel. This causes another problem.
In U.S. Pat. No. 6,043,679, a level shifter utilizing only one input clock signal to generate a corresponding output clock signal is disclosed. The level shifter is able to change the input clock having the 0˜5V voltage levels into the output clock having the −10˜10V voltage levels. The above-mentioned one-clock level shifter has to be biased by the −10V and 10V biases. That is, if the 10V and 0V biases are utilized as the DC levels, because the 0V biases may not drive the level shifter well, the clock shifter will not work so correctly.